(1) Field of the Invention
The present invention generally relates to a clock switching apparatus, and more particularly to a clock switching apparatus selecting a clock signal from a plurality of clock signals without a signal break.
(2)Description of the Prior Art
In recent communication systems, a plurality of clock sources, generating clock signals, are provided and one of the clock sources is selected in order to establish the synchronization of the entire communication system and improve the reliability thereof. Examples of such clocks for use in system synchronization are a master clock generated and output by an exchange office, an internal clock generated in each terminal, and a clock extracted from a signal transmitted from a transmission line.
FIG. 1 shows a conventional clock switching apparatus. As shown, the clock switching apparatus is made up of two frequency dividers 10-1 and 10-2, a selector 12, a phase synchronizing circuit 13 and a differentiating circuit 14. The clock switching apparatus shown in FIG. 1 receives two identical master clock signals CLKa and CLKb from an exchange office (not shown), and selects either the clock signal CLKa or CLKb. Each of the identical master clock signals CLKa and CLKb, which are also illustrated in FIG. 2, has a frequency of, for example, l.5 MHz. The frequency dividers 10-1 and 10-2 frequency-divide the clock signals CLKa and CLKb, respectively, and output respective frequency-divided clock signals DCLKa and DCLKb shown in FIG. 2 to the selector 12. Each of the frequency-divided clock signals DCLKa and DCLKb has a frequency of, for example, 8 kHz. Normally, the selector 12 selects, for example, the clock signal CLKa.
Signal-break detection signals DETa and DETb are supplied to the selector 12. The signal-break detection signals DETa and DETb switch to an active level when the clock signals CLKa and CLKb are broken. The selected clock signal is input to the phase synchronizing 13 and the differentiating circuit 14. The phase synchronizing circuit 13 compares the phase of the selected clock signal with the phase of an output clock signal which is output to a circuit of the next stage, and synchronizes the output clock signal with the selected clock signal. The differentiating circuit 14 detects a switching point at which the selected clock signal is changed, and outputs a reset signal R to the frequency dividers 10-1 and 10-2. In response to the reset signal R, the frequency dividers 10-1 and 10-2 are reset, so that they are synchronized with each other.
Assuming that the clock signal CLKa is broken at time t.sub.1, as shown in (C) and (D) of FIG. 2, the selected clock signal from the selector 12, labeled SEL, shown in (F) of FIG. 2 is broken. It will be noted that it is necessary to provide for a predetermined period of time T (equal to, for example, 10 ms) in order to detect the break of the clock signal DETa. Thus, as shown in (G) of FIG. 2, the detection signal DETa related to the clock signal CLKa switches to the active (high) level after the period T from time t.sub.1. In response to this change in the detection signal DETa, the selector 12 switches to the frequency divider 10-2, so that the supply of the clock signal is restarted, as shown in (F) of FIG. 2.
It should be noted that the input terminal of the phase synchronizing circuit 13 is continuously supplied with the low-level signal (or high-level signal) during the period T. Thus, the phase of the output clock signal generated and output by the phase synchronizing circuit 13 changes abruptly. This abrupt change in the phase of the output clock signal causes various problems, such as line circuit errors and decision errors.